1. Field of the Invention
The present invention generally relates to a method for forming a dynamic random access memory (DRAM), and more particularly to a method for fabricating an inner-cylindrical capacitor in DRAM.
2. Description of the Prior Art
Modern semiconductor for fabricating technique in an ultra large scale integration (ULSI) highly increases the circuit density on a chip. The increase of circuit density causes the downsizing of devices and the increase of device packing density.
Although commonly referred to as semiconductor devices, the devices are fabricated from various materials, including conductors (e.g., aluminum, tungsten), non-conductors (e.g., silicon dioxide) and semiconductors (e.g., silicon). Silicon is the most commonly used semiconductor, and is used in either its single crystal or polycrystalline form. Polycrystalline silicon is often referred to the silicon is adjusted by adding impurities.
The integrated circuit devices with their various conductive layers, semiconductor layers, insulating layers, contacts and interconnects are formed by fabrication processes, including doping processes, deposition processes, photolithorgraphy processes, etching processes and other processes.
Demand of dynamic random access memory (DRAM) has rapidly increased owing to widespread use of integrated circuits. Each cell of DRAM includes transistors and a capacitor, which is used for the purpose of charge storage. As DRAM becomes highly integrated, the area occupied by the capacitor of DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor owing to its smaller electrode surface area. In order to reduce the cell dimension and yet obtain a high capacitance, the cylindrical-shaped capacitor, which includes an inner surface in addition to an outer surface, was disclosed to increase the surface area of the capacitor electrode.
DRAM is a device broadly used in electronic industry for data storage due to the characteristic of increased circuit density in an integrated circuit (IC). This stored information or message is determined by the charges stored in an internal capacitor of a memory cell. The access of data is performed by operating the read/write circuit and the peripheral memory in a chip. A single DRAM cell comprises a field effect transistor (FET) and a capacitor as a bit for representing a binary data.
The basic DRAM cell is usually comprised of a transfer gate transistor and a connected capacitor. Charges are stored in the capacitor section of DRAM, and are accessed via the transfer gate transistor. The ability to densely pack storage cells, while still maintaining sufficient stored charge, is a function of the type and structure of the capacitor section of DRAM. Two iterations of capacitors are presently being manufactured. A trench capacitor, in which charge is stored vertically in a structure fabricated by etching a deep trench in a substrate, has found use where high DRAM densities are desired. This type of capacitor, although eventually needed for the higher density DRAM, is however costly to fabricate, regarding the trench etching, trench filling and planarization processing. The advantage of trench capacitor is that the device surface is much more plane after the capacitors finished. Moreover, the processes for dielectric materials used therein, such as nitride or oxidate nitride, have been well developed. However, it requires deep trenches to provide sufficient capacitance, which increases the difficulties of etching and trench filling. Trench capacitors take another advantage of the vertical space available in a semiconductor substrate material, thus reducing the overall layout size of a semiconductor device on the substrate surface.
The disadvantages often associated with such structures are the complexity and number of the process steps required in fabrication. For example, in order to utilize vertical space, trenches for forming capacitors should be fabricated deeper. To form deeper trenches, we need more than one step for forming trench. Furthermore, as the trench is formed deeper the trench also becomes narrower, resulting in manufacturing difficulties during subsequent processing. Another disadvantage with a deep, narrow trench is that the effective capacitance of the cell is required to below a desirable amount.
A second type of capacitor used in DRAM technology is stacked capacitor cell. In this design two conductive layers, such as polycrystalline silicon, are placed over a section of the transfer gate transistor, with a dielectric layer sandwiched between the polycrystalline layers. The stacked capacitor iteration has been used extensively in the industry, with emphasis placed on reducing the cost, while still increasing DRAM chip densities.
One ongoing goal of semiconductor design and fabrication is to reduce costs. Cost reduction is essential to ongoing success in the field. One manner of reducing costs is to eliminate or optimize steps in the semiconductor fabrication process such as without top electrode mask for forming inner-cylindrical capacitor. In doing so, it is important to maintain or improve device and process efficiency and effectiveness.
In accordance with the present invention, a method is provided that top electrode mask of inner-cylindrical capacitor can be omitted.
It is an object of this invention that substantially can reduce the cost for fabricating inner-cylindrical capacitor.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention directed toward a method for fabricating a capacitor is proposed. An etch-stop layer and an etch-buffer layer are formed sequentially on the substrate. Then, a first photoresist layer is defined on the etch-buffer layer to form a bit line. After the first photoresist layer is removed, a silicon dioxide layer, a first conductive layer, and an insulating layer are formed sequentially on the substrate, wherein the first conductive layer is a first lower electrode of the inner-cylindrical capacitor. Then, a silicon dioxide layer, a first conductivity layer, and an insulating layer are etched sequentially and then etched stop on the etch-buffer layer. Next, an etch-buffer layer is etched stop on the etch-stop layer. Therefore, a trench structure is formed on the substrate. Then, a first polysilicon spacer, as a second lower electrode, is formed on the floor and sidewall of the trench. Then, a thin dielectric layer is deposited on the sidewall of the first polysilicon spacer. The dielectric layer consists of silicon nitride and an oxide layer. Next, a second polysilicon spacer is formed on the sidewall of the dielectric layer. Then, a polysilicon layer is filled within the trench structure and excess polysilicon layer is removed by chemical mechanical polishing (CMP). Then, a polysilicon plug as a top electrode is formed in the trench.